Rechnergestützter Schaltungsentwurf Digital / Computed Aided Digital Circuit Design

Part: Engross VHDL

1.  VHDL Course:

Contents
Chapter 1: VHDL: Getting Started,
Chapter 2: VHDL: Data, Data short form
Chapter 3: VHDL: Modeling,
Chapter 4: VHDL-AMS Fundamentals
Chapter 5: Synthesis
Chapter 6 = Appendix A:  Some Basics of Digital Circuit Design.
Chapter 7 = Appendix B: Some important Standard Package Extractions (standard, textio, ieee.std_logic_1164).
Chapter 8: Felder, Wellen, Leitungen, Fundamentals to understand effects on transmission lines (German)

2.  ASCII.vhd:

For the VHDL code examples see -> PRE2 (practical training for RE2)

Chapter 1:
1_getting_started.vhd -- source code examples of chapter 1
1_deferred_constants.vhd -- to be translated later in chapter 1

Chapter 2:
2_data.vhd -- source code examples of chapter 2
2_tst_roundoff.vhd -- file to test the roundoff-behaviour of integer and physical data types. (TIME may behave different on some simulators, e.g. the ModelSim.)

Chapter 5:
5_asynchronous_capturing.vhd -- source code of chapter 5 for an asynchronous signal capturing circuit

3.  Other Sources: Qualis_VHDL_Language_QuickReferenceCard,  Qualis_VHDL_StdLogic1164_QuickReferenceCard