Veröffentlichungen

Als Autor

C.V. Schimpfle, P. Rieder, J.A. Nossek: „A Power Efficient Implementation of the Discrete Cosine Transform“, Proceedings of the 31st Asilomar Conference on Signals, Systems and Computers. Pacific Grove, California, USA, pages 729-733, November 1997. C.V. Schimpfle, S. Simon: „Estimation and Reduction of Glitches in Data Paths“, Technical Report No. TUM-LNS-TR-97-4, Technische Universität München, February 1997. C.V. Schimpfle and S. Simon: „Estimation and Reduction of Spurious Switching Activities in Static CMOS Circuits“, International Journal of Electronics and Communications, AEÜ, 51(6), pages 296-303, November 1997. C.V. Schimpfle and S. Simon: „Signed Digit CORDIC Implementation for Low Power Applications“, Technical Report No. TUM-LNS-TR-97-2, Technische Universität München, February 1997. C.V. Schimpfle, S. Simon, J.A. Nossek: „Device Level Based Cell Modeling for Fast Power Estimation“, Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS'99, Orlando, Florida, USA, May 1999 . C.V. Schimpfle, S. Simon, J.A. Nossek: „High-Level Circuit Modeling for Power Estimation“, Proceedings of the 6th International Conference on Electronics, Circuits and Systems, ICECS'99, Pafos, Cyprus, September 1999 . C.V. Schimpfle, S. Simon, J.A. Nossek: „Low Power CORDIC Implementation Using Redundant Number Representation“, Proceedings of the IEEE International Conference on Application Specific Systems, Architectures and Processors, ASAP'97, Zürich, Switzerland, pages 154-161, July 1997. C.V. Schimpfle, S. Simon, J.A. Nossek: „Optimal Placement of Registers in Data Paths for Low Power Design“, Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS'97, Hong Kong, pages 2160-2163, June 1997. C.V. Schimpfle, S. Simon, J.A. Nossek: „Optimizing Sequential Circuits for Minimum Glitching Activity“, Proceedings of the European Conference on Circuit Theory and Design, ECCTD'97, Budapest, Hungary, pages 1332-1336, 1997. C.V. Schimpfle, A. Wróblewski, J.A. Nossek: „Transistor Optimization for Minimizing Switching Power in CMOS Circuits“, Technical Report No. TUM-LNS-TR-99-4, Technische Universität München, July 1999. C.V. Schimpfle, A. Wróblewski, J.A. Nossek: „Transistor Sizing for Switching Activity Reduction in Digital Circuits“, Proceedings of the European Conference on Circuit Theory and Design, ECCTD'99, Stresa, Italy, August 1999. C.V. Schimpfle: „Entwurfsmethoden für verlustarme integrierte Schaltungen“, Dissertation, Shaker Verlag Aachen, August 2000. C.V. Schimpfle, J. Kirchner: „A Step-Down Conversion Concept for a PWM-mode Boost Converter“, Power Electronic Specialists Conference, PESC'03, Acapulco, Mexico, June 2003.

Als Mitautor

P. Rieder, C.V. Schimpfle, and J.A. Nossek: „Realization of Multiwavelet-Based Transform Kernels for Image Coding“, Proceedings IEEE International Symposium on Circuits and Systems, ISCAS'98, Monterey, California, USA, 1998. P. Rieder, S. Simon, and C.V. Schimpfle: „Application Specific Efficient VLSI Architectures for Orthogonal Single- and Multiwavelet Transforms“, Journal of VLSI Signal Processing Systems, 1999. S. Simon, P. Rieder, C. Schimpfle, and J. A. Nossek: „CORDIC-Based Architectures for the Efficient Implementation of Discete Wavelet Transforms“, Proceedings IEEE International Symposium on Circuits and Systems, ISCAS'96, Atlanta, GA, USA, 1996. S. Simon, C.V. Schimpfle, M. Wróblewski, and J.A. Nossek: „Retiming of Latches for Power Reduction of DSP Designs“, Proceedings IEEE International Symposium on Circuits and Systems, ISCAS'97, Hong Kong, pages 2168-2171, June 1997. A. Wróblewski, C.V. Schimpfle, and J.A. Nossek: „Automated Transistor Sizing Algorithm for Minimizing Spurious Switching Activities in CMOS Circuits“, Proceedings IEEE International Symposium on Circuits and Systems, ISCAS 2000, Geneva, Switzerland, May 2000. A. Wróblewski, C.V. Schimpfle, O. Schumacher, J.A. Nossek: „Minimizing Spurious Switching Activities with Transistor Sizing“,VLSI Design, Vol. 15 (2), pages 537-545, 2002.