This seems to be sophitsticated stuff!

 

Tabel of contents

 

1. MESFET models based on GaAs

1.1 An analytic model of a MESFET based on physical principles

1.1.1 MESFET Device Characteristics

1.1.2 The Schottky Junction

1.1.2.1 Depletion Height and Capacitance

1.1.2.2 Current Flow Across a Schottky Junction

1.1.3 The Drain current

1.1.3.1 Field dependent mobility and velocity

1.1.3.2 Electric Field in a MESFET

1.1.3.3 Overshoot Effect

1.1.3.4 Analytic Drain current description

1.1.4 The Gate current

1.1.5 Capacitive Currents

1.2 Capacities

1.3 Parasitic Elements

1.3.1 Parasitic Capacities

1.3.2 Parasitic Resistance

1.4 Models

1.4.1 Charge Based Model for Circuit Simulation

1.4.2 Capacitance Based Model

1.4.3 Small Signal Model

1.4.4 Empirical Model

1.5 Summary

2. Conclusion

 


 

1. MESFET models based on GaAs             

A MESFET (Metal-Semiconductor Field Effect Transistor) is considered a unipoloar transistor to distinguish it from the bipolar junction transistor where electrons and holes participate in the current flow. The rectifying contact is formed by bringing the semiconductor material in contact with the gate metal to form a Schottky barrier. As illustrated in Figure 3.0-1, the MESFET is composed of a narrow semiconducting channel with two ohmic and one rectifying metalcontacts, because each material has its own Fermi energy, the Fermi levels adapt themselves to a common level at thermal equilibrium. Through this effect, a depletion layer under the gate is formed. The thickness of this depletion layer can be controlled by an applied gate voltage, therefore a MESFET can be regarded as a voltage controlled resistor. Sine the depletion layer is significant in dimension even without an applied gate or drain voltage, the type of transistor can be defined by controlling either the channel thickness or the donor impurity concentration ND in the channel region. The H-GaAs-III process of Vitesse defines the kind of transistor by controlling the donor concentration. The process follows these steps: an undoped buffer layer of GaAs is epitaxially grown on top of a semi-insulation substrate. After depositing a dielectric cap, the active region with a donor concentration of about ND = 1016 cm-3 is defined by ion implantation. This implantation doping is equal to that needed for the enhancement device. To get depletion devices a additional implantation with a different mask is done. After this the gate metal is deposited and defined. An implant with impurity concentration of about ND = 1018 cm-3 will define the source and drain areas. After a activation anneal the source and drain metal can be deposited and sintered. The Vitesse GaAs MESFET is shown in Figure 5.0-1.

     

    Figure 5.0-1: MESFET Vitesse H-GaAs-III Design

     

GaAs MESFETs have many advantages. Above all the electron velocity at low field is sufficiently high so that high switching speed and therefore high cutoff frequencies can be achieved. An additional high input impedance, negative temperature coefficient at high current level and thermal conductivity, low resistance and low I× R drop along the channel height so that GaAs MESFETs are especially useful for low-noise amplification, high-efficiency power generation and high-speed logic application.

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1.1 An analytic model of a MESFET based on physical principles

By describing the physics of the MESFET analytically, it becomes rapidly obvious that this model is far from usable for both circuit design and circuit simulation. By changing one of the node voltages the whole model has to be recalculated. This means solving nonlinear algebraic equations by iteration. For a transient simulation this must be done on every for every time point again and again. That includes currents and charges. By developing bigger circuits normally every computer rapidly reaches its limitations by using this model.

On the other side there are empirical models. An empirical model describes the device characteristics by using a simple analytic equation. These equations may not have any physical origin, rather they describe the device behavior in a mathematical sense. An important advantage of an empirical models is their flexibility. The equations can be fitted over given parameters. However the disadvantage of such models is that the equations may lead to non-physical results because they are often too simple. The empirical model however makes it possible to use it in simulation software like HSPICE.

The physical models are based on the device materials, geometry and processing parameters such as doping concentration, carrier mobility and carrier velocity, doping profile and doping concentration, barrier height, layer thickness and device dimensions. These models are useful for basic research on a transistor. One famous physical FET model is the classical Shockley model which is derived from the Poisson and current-continuity equations.

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1.1.1 MESFET Device Characteristics

Figure -1 shows a schematic model of a depletion MESFET with the basic device dimensions. L is the term for the gate length and W the term for the gate width. The parameter "a" is the channel height and "h" is the height of the depletion zone at a specific point under the gate. The MESFET consists of an active channel, contacted with higher doped areas called source and drain. The third electrode is the gate. The applied drain voltage VD and gate voltage VG are referenced to the source which is normally grounded. When a positive voltage VD is applied, a physical current from source to drain will flow. In this way the terms drain and source explain themselves. The gate controls the current under the gate by varying the depletion height h so that a MESFET can be basically regarded as voltage controlled resistor.

        Figure -2: abstract MESFET model

Figure -3 shows a typical I-V diagram of a depletion MESFET. The drain current ID is plotted against the drain voltage for various gate voltages. The linear region corresponds to the model of a voltage controlled transistor. Above all, for voltages << VD sat, VSD is direct proportional to the drain current ID. At the saturation region ID remains nearly constant because the drift velocity has reached its saturation. ID can so be regarded as independent of VSD. At the break down region, a small increase of VSD causes a rapid increase of the drain current ID because the electron energy is big enough to ionize other atoms provide additional electrons. This is called the avalanche effect.

        Figure -4: I-V characteristic of a depletion MESFET

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1.1.2 The Schottky Junction

When a metal and a semiconductor with therefore different Fermi energy levels are brought in contact with each other, the Fermi energy of each material will line up to a common level. In case on a n-type semiconductor the Fermi energy of the semiconductor is larger than the Fermi energy of the metal. Because there are many empty energy states in the metal, electrons with sufficient energy will flow into the metal taking the energy state. By leaving the semiconductor there will be unfilled energy states left in the semiconductor. Moreover, because a contact between the two different materials can never be ideal, the presence of chemical defects or broken bonds will cause large numbers of unfilled so called surface states. These free states will be filled by electrons from the semiconductor bulk. This provide a positive charge under the junction and a depletion region is formed. During this process the valence and conduction band is bent by the positive depletion charge preventing more electrons to take metal or surface states. Because the number of unfilled surface states is high, the metal side is assumed to be constant. From Figure -5, the following equation can be found:

 

-q× VB = -q× Vbi + EC - EF

 

Figure -6: Band Diagram of metal/n-type semiconductor junction

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1.1.2.1 Depletion Height and Capacitance

Once the relationship between valence and conduction band of the semiconductor with the Fermi level of the metal are known, it can be used as a boundary condition on the solution of Poisson’s equation in semiconductors. Under the abrupt assumptions that r » q× ND for x smaller than depletion height, and r » 0 and dV/dx» 0 for x larger than depletion height. The results are summarized below

        Equation -1

        Equation -2

             Equation -3

where VG is the applied gate voltage, VB is the barrier height and Vbi the built in voltage given by , ni is the intrinsic carrier concentration. It should be noted that for GaAs the barrier height VB>>k× T/q for all cases of metals to be contacted. Table 1 shows the barrier heights for different materials. For the n-type of GaAs, the barrier height is nearly the same value.

        Semiconductor

        Type

        Ag

        Al

        Au

        Pt

        Ti

        W

        GaAs

        n

        0.88

        0.80

        0.90

        0.84

        -

        0.80

        GaAs

        p

        0.63

        -

        0.42

        -

        -

        -

        Table 2: Barrier heights in volt

The maximum field strength occurs at the semiconductor-metal interface, x=0. The space charge QSC per unit area of the semiconductor is given by

        Equation -4.

From this equation the depletion capacitance CDP can be derived from

        Equation -5.

The last equation assumes that the depletion zone separating the metal and the neutral semiconductor can be regarded as a parallel plate capacitor.

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1.1.2.2 Current Flow Across a Schottky Junction

The Schottky junction represents a diode. The current transport in this contact is mainly due to majority carriers. In the Schottky diode there are four kind of carrier transport where the thermionic emission current is the dominant one. The four processes are

(1)

transport of electrons from the semiconductor over the potential barrier into the metal at room temperature,

(2)

quantum-mechanical tunneling of electrons through the barrier that is only important for heavily doped semiconductors,

(3)

recombination in the space-charge region,

(4)

hole injection from the metal to the semiconductor.

The active region is moderately doped with a concentration between 1016-1017 cm-3, the tunneling effect (2) can be neglected. Effects (3) and (4) can also be neglected because this are recombination processes. The fact that the minority concentration is limiting the recombination process gives an idea about the magnitude of these currents.

The thermic emission current, also called gate current, is given by

Equation -6,

where A is the area of the junction, R the "Richardson’s constant", m* the effective mass, h the Planck’s constant and k the Boltzmann’s constant. For the Richardson’s constant, usually experimental values are used, not the calculated one. The equation for the gate current gives a good idea how the built in voltage is related to the applied gate voltage.

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1.1.3 The Drain current

The following points will derive a expression for the drain current as a function of the terminal voltages. Firstly the Schottky junction and effects like the carrier mobility and overshoot will be discussed. To get a mathematical description assumptions and approximations have to be made. The n+-regions are regarded as perfect conductors and the built-in potential at the n+/n-interface is zero. The substrate is regarded as perfect insulator so that the surface charge at the n-GaAs/GaAs is zero. Due to convention VD is greater than and equal to VS.

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1.1.3.1 Field dependent mobility and velocity

The conduction band minimum in GaAs, the G -valley, is made up of a single valley with a very light effective mass m*=0.067m0 and at a energy of 0.3eV higher there is a heavy mass valley called the L-valley with an effective mass of m*=0.22m0.

 

 

At fields lower than 3 kV/cm, the electrons are primarily in the G -valley where they have low mass and therefore a high velocity. The peak velocity in pure GaAs can reach a value of about 2.2E7 cm/s at a field of 2.5 kV/cm. As the field increases, the upper valley is more and more occupied by electrons. Since the upper valley electrons have a bigger effective mass, the electron velocity decreases even through applying higher electric fields. The average velocity saturates at a value of about 0.7E7 cm/s if the carriers a mainly concentrated at the L-valley.

Walukiewicz et [8] gives the following empirical description of the mobility of carriers in a semiconductor dependent of doping concentration and temperature. The average error is about 4% however it is longer at lower fields.

Q =NA/ND range [0, 0.9]

n range [1015, 5× 1018] cm-3

a =0.53+0.03× Q

m max =8200[300K]

 

for Q <0.2: nref=9.63× 1018× Q 3-4.2× 1018× Q 2+3.7× 1017× Q +9.85× 1016 cm-3

for Q >0.2: nref=1017.07× (1-Q )^0.04 cm-3

for Q <0.2: m min=-16500× Q 3+17450× Q 2-8080× Q +2750

for Q >0.2: m min=2350× (1-Q )1.45

 

Equation -1

Moreover he wrote the dependence of mobility of the temperature in format as a power law. The problem in doing this is that the optical scattering rates do not scale as the power law so that for large doping concentrations n>1017 cm-3, the Fermi function does not have an exponential behavior. The thermal dependence is given by

 

Equation -2.

The parameter s for n [1017, 1018] cm-3 is in the range of s=0.5± 0.1 in a modern MESFET.

There are many ways to analytically describe the velocity of carriers. All of them have in common that they are empirical models. Many models for the drain current support the so called linear model. In this model it is assumed that the carrier mobility is constant so that the drift velocity of carriers becomes to . This linear approach can only be made because the scattering of electron at fields lower than 2.5 kV/cm is low so that the drift velocity increases linearly with field. Since this model is a simple linear equation it makes further mathematical description much easier. This model is limited to a electric field lower than 2.5 kV/cm. This not a very big restriction since the main application of GaAs takes place in low fields to achieve high carrier velocity. Moreover such electric fields can only be found at very short channel devices L<0.25m with a source-drain voltage of 1V when the channel is entirely open. This means that the electric field is not constant in the channel region. Because of carrier distribution under the pinch-off point electric fields can be achieved of 10 kV/cm so that models based on the linear model will lead more and more to incorrect results.

 

Another way do describe the drift velocity is that the electric field vs. vD is described empirically so that to each value of the electric field a good value of vD is available. This has advantages for models that are supporting fields around 2.5 kV/cm. Moreover the field dependent mobility of carriers is also included by describing the curve. A disadvantage of this model is that the equation only delivers the saturation velocity. The transport of electrons is a dynamic process over time and effects like the overshoot will be disregarded. At this point it should be mentioned that electrons never reach steady state in a normal MESFET. Moreover because the equation is not linear the mathematical handling of further models including this model will be intractable. The drift velocity vD can be described after myself as

 

Equation -3.

 

This empirical description only depends on the extreme points of the curve. Corrections for a better fit in specific areas can be made by changing the exponent of e 2. For low fields the equation becomes to . This confirms the linear model. Furthermore could be replace by m , however the equation would become again dependent of the mobility of carriers. If a dynamic temperature model should be done this could be a interesting option. For the drain current a third model will be chosen, as discussed later, that assumes that the electrons never reach steady state and stay at the peak velocity. Figure 5.1-9 shows the graph of Equation 5.1.3-3.

Figure -9: Calculated Drift Velocity Model

 

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1.1.3.2 Electric Field in a MESFET

 

 

Figure -11 shows a channel cross section of a GaAs MESFET with a applied gate voltage of VG=-1V so that the channel is driven towards pinch off. The source-drain voltage is 3V. The drain current is in saturation. The narrowest channel opening is under the drain end of the gate. Under this point a statistic capacity is built up through velocity behavior of electrons in GaAs in high field environment. Because the resistance under the end of the gate is the highest most of the voltage will fall off at this point and therefore there will be the highest electric field. If an electron is flowing in this area it will be accelerated through this field. Since the behavior of electron shown in Figure 5.1-9 electrons reaches saturated velocity which is lower in this region than the peak velocity. Because more electrons are coming in than out a heavy electron accumulation takes place. After passing the peak of the electric field the opposite occurs. After the peak the channel is opening very fast and therefore the electric field is decreasing. Because the electric field is becoming smaller the electrons can again reach there peak velocity causing a strong depletion layer. In this way a statistic capacitance is built up causing a new electric field that reinforce the present electric field.

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1.1.3.3 Overshoot Effect

 

 

Figure -13 shows the behavior of electrons in a high electric field. Before the carriers enter the high field area they remain in equilibrium. By entering the high field area which is much higher than the electric field for the peak velocity, the electrons are accelerated to a velocity which is more than two times higher than the peak velocity. In this area the electrons are in nonequilibrium. After a distance of 1 m m the electrons reach equilibrium again. In order to use this effect as an advantage the gate has to be short. In this way the overshoot effect shortens the transit time of the carriers in a direct ratio and therefore improves the high-frequency response. This effect also takes place in the carrier accumulation under the pinch off point of the gate as previously mentioned and therefore reinforces the accumulation effect. Because the effect is not abrupt as described here, the carriers will reach not such high velocity.

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1.1.3.4 Analytic Drain current description

First of all a uniform charge distribution under the gate is assumed. For the depletion layer width under the gate, the abrupt junction expression formerly used for the Schottky contact is given by

, where Vbi is the built in potential given by . V(x) is the applied drain voltage at x with respect to the source. The gate voltage VG is negative in n-channel devices with respect to the source. The depletion height at the source side of the gate is given by

and for

Equation -4.

The pinch off voltage can be found for y2=a. Putting in this term results in

 

, and Equation -5.

Equation -6.

 

The last term can be defined as the pinch-off voltage so that VGD becomes . The pinch-off voltage VP is proportional to the second power of the thickness of the channel height so that this value is very sensitive to dimensional variations. The value of VGS at cut-off is called the threshold voltage, VT. The threshold voltage depends on doping concentration, channel height and built-in voltage. By controlling the device parameters, the device can be determined as enhancement or depletion.

The current density along the channel is given by the ohmic-law equation J(x)=s (x)× E(x) or J(x)=q× ND× m × E(x), where J(x) is the current density along the channel, E(x)= dV/dx the electric field along the channel and m the mobility of the carriers previously mentioned. The current equation through the channel is therefore,

 

.

Equation -7

In the following drain current description ND (x) is assumed as uniform and completely ionized. The term [a-h(x)] is the channel height and v(x) is the function for the electron velocity dependent of the longitudinal electric field. As previously mentioned, the electron never reach saturation or steady state velocity. Since the described function for the accurate value is difficult to handle, an easier function is introduced. For this function it is assumed that after reaching the peak velocity at x=LC, the carriers remain in the same velocity until they arrive at the drain. This function is approximated by

Equation -8.

 

Figure -14: assumed velocity-field

EP is a parameter and is used to adjust the curve to the given values. E is the longitudinal electric field that can be expressed by E=dV/dx. For E<<EP v(E) becomes v(E)=m × E. At E=EC, the function becomes constant with the value vS.

The drain current then becomes

 

Equation -9.

To approach an analytic expression, the two region electric field in Figure 5.1-15 is assumed. In region 1, the longitudinal electric field is small compared to the transverse field. By lowering the gate voltage, VSG is decreased and VGD is simultaneous increasing so that a pinch-off can occur. This point is described as x=LC. Because the source-gate voltage in this case is low compared to the gate-drain voltage, the electric field between source and gate is low. This can also be explained by a resistor model. The area over the pinch-off point represents, because of the small channel at this point, a high resistance area compared to the resistance between source and the pinch-off point LC. Therefore the most voltage drop will occur in the area over the pinch-off point. The depletion height can therefore be described by a one-dimensional Poisson’s equation. In region 2, the longitudinal field is no longer small and a two-dimensional description of the potential is required.

 

Figure -15: assumed field and velocity

 

First region 1 will be considered. We get

 

Equation -10

after separating the variables from Equation -11 and integrating from x=0 to x=LC on one side and from V=VS to V=VC on the other. The remaining unknowns are LC and VC. As mentioned, LC and VC are the values for the possible pinch-off point. For long channel or low field devices, the pinch-off case does not occur and the electric field never reaches the value EC. In case the electric field is much smaller than EP, the assumed two region field dependent velocity simplifies to a linear model previously mentioned as v=m × E. In this case we get after separating and integrating following closed expression with no unknowns for the drain current:

 

Equation -12

We now consider the Region 2. The electron drift velocity has a constant value of vS. The depletion height at the boundary of Region 1 to Region 2 is

Equation -13

which is assumed to be constant through the rest of the remaining channel. The unknown variable is VC. The drain current is, formerly assumed constant velocity and constant channel height,

 

Equation -14.

The remaining problem are the unknowns LC and VC. To solve this problem we need two equations. One can be already derived by putting the equation for the boundary case of Region 1 and Region 2 equal. The second equation for the unknowns can be achieved by solving Poisson’s equation at the region around the drain. There the voltage correspond to the applied drain voltage and the electric field is sufficiently high and satisfies therefore Poisson’s equation:

 

Equation -15.

This will bring us to a differential equation with a homogeneous and a particular solution. By solving this problem and combining with the formerly achieved equation, we will get two equations for the unknowns LC and VC. Because the mathematical description would go in to too much detail, only the results are shown.

 

Equation -16

Equation -17

The first equation can be solved by Newton iteration to get VCS. LC can then be found by solving equation 2.

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1.1.4 The Gate current

In the derivation of the drain current, the gate current was neglected. Indeed if the gate voltage is sufficiently low, the thermionic emission current across the Schottky junction is negligible. If the gate is driven with a large positive voltage, a gate current will flow. This gate current influences the performance of enhancement transistors. More than the depletion transistor, the achieved results for a two region model depends on the work of Chandra [2] by using following circuit model:

        Figure -16: current model of a MESFET including the gate current

Out of this two region current model we can derive

IG=IGS+IGD

ID0=ID-IGD Equation -1

IS0=ID+IGS

ID=IC+IGC

As previously mentioned, the current through a Schottky junction can be expressed by

        Equation -2.

For a applied source-drain voltage, these expressions become

        Equation -3.

By integrating the equation for the gate current we get

        Equation -4.

The integration constant I’GD can be determined by the assumption that in Region 2, the current IC is given by the total longitudinal current plus the total gate current so that we can write

        Equation -5.

After Chandra [2], it is assumed that the channel voltage V(x) is a linear function of x. V(x) becomes than to

        Equation -6.

Therefore the total gate current is given by

        Equation -7.

Without mathematical guide IGC is given by

        Equation -8.

The unknown parameters are now E1 and IS0. IS0 is given by

        IS0=ID+IG(E1)-IGC(E1)-I’GD(E1).

ID is the drain current derived formerly.

         

E1 must satisfy the following requirements in Region 1. At x=0, the current I(x=0)=IS and the electric field has the value E1. This parameters can be inserted into the drain current equation for Region 1. Solving for E1, yields

        Equation -9.

The equation IS=ID+IG(E1)-IGC(E1)-I’GD(E1) can be solved with the last equation by iteration. The end result will be after simplifications

        Equation -10.

E1 can be found by substituting the last equation into equation the equation for E1. By doing this we get the first iteration for E1. This E1 is then inserted in IS0=ID+IG(E1)-IGC(E1)-I’GD(E1). In this way we get the first iteration of IS0. The value of IS0 is than inserted into the equation of E1 to get the next iteration of E1. This procedure will be repeated until the iteration converges. By calculating E1 all gate currents can be described.

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1.1.5 Capacitive Currents

So far the static or DC current expression has been derived. For the following description, a logical circuit is assumed. The used signal varies between a logical 0 and a logical 1. That means a large change of the terminal voltages and therefore there will be capacitive currents at the terminals caused by the surface charge on the gate and the charge in the depletion region along the channel.

The terminals are described as

,

which reduces to

Equation -1.

QD, QG and QS are the terminal charges which cause the fast changing capacitive currents at the terminals in which ID0, IG and IS are the DC or slowly varying part of the respective currents. The dependence of the charges will be derived under point 3.2. Equation 3.1.5-1 gives a quasi-static description of the terminal behavior of a MESFET. This description is most suitable for circuit simulation.

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1.2 Capacities

For the derivation of the terminal charges, the two region model will be used. Figure -1 shows the depletion regions under the gate. The following derivation for the capacity in a MESFET does not regard the fringe capacities resulting from the fields beyond the borders of the gate. Figure 3.1.1-1 gives an imagine of the size of these fringe capacities.

 

Figure -2: depletion region under the gate after the two region model

In the shown two region model, qS is the surface charge density on the gate and is given by, for Region 1

Equation -2

and for Region 2

Equation -3

which was obtained formerly.

As the terminal voltages are changing with time, the depletion height will change. By changing the depletion height, the amount of charge on the gate will change and with it, a displacement current will occur which adds to the total channel current emerging at the source and drain terminals. The current continuity equation becomes to

Equation -4

By integrating this equation with the boundary condition i(0, t) =-iS(t) for the source yields,

Equation -5.

Integrating over the channel, we get

Equation -6.

By comparing this equation with Equation -7 we can derive the quantity inside the brackets as the terminal charge at the source so that QS becomes

Equation -8.

This can be done in a similar manner for the drain charge. The drain charge is

Equation -9.

 

The total charge on the gate is QG=-QD-QS and hence

Equation -10.

In order to achieve a tractable mathematical solution, it is assumed that the surface charge will be fairly insensitive to the fine structure of h(x). Hence h(x) is approximated with a linear function of x in Region 1. Therefore, we get

 

Equation -11

with

Equation -12.

We get in this way

 

Equation -13

 

Equation -14

By expanding this expressions we get

 

Equation -15

 

Equation -16

 

Equation -17

It should be noted what hC, hS and LC are functions of the terminal voltages. Therefore when the voltages are specified, the terminal charges QD, QS and QG can be calculated.

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1.3 Parasitic Elements

Parasitic Elements caused by impurity concentration and crystal defects do not strongly affect micron devices. This effects strongly increase for submicron devices. Since the ratio between parasitic and natural elements becomes larger, it can be the limiting factor for semiconductor devices. Because the edges or fringes of a device are never ideal, most defects occur in this area. By downsizing a device, the ratio between volume and device surface is increased and therefore the ratio between the normal given errors and the edge errors is also increased.

      Figure -1: intrinsic model with interelectrode capacitance

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1.3.1 Parasitic Capacities

In order to reduce power consumption, improve frequency response and cut-off frequency, very small area devices are generally used. For these very small devices, parasitic capacities will affect more and more the frequency performance of devices by adding to the input or output capacity. Parasitic capacities are generally independent of the gate width and can be caused by defect density, crystal defects and other fringe phoneme. This explains the dependence of the size of the device. When the devices become smaller, the ratio between parasitic capacities and input capacities reach a critical value. Gain bandwidth product and propagation delay are given by

 

Equation -1

,

where t is the transit time given by or R× C, the average transit time.

 

Based on these two relations, the following statements can be made:

 

  • when CP becomes greater than CIN, the performance is greatly reduced
  • the power delay is proportional to the transit time t ; by increasing the average velocity of the carriers, t is reduced and the effect of the parasitic capacity can be buffered

 

 

 

Outside of the intrinsic region of a MESFET, there are additional sources of parasitic capacitance. These capacitances have there origin in the physical dimension of the device or, if we go one level further, in interconnection with other devices. Figure 0-2 illustrates the location of such parasitic capacities. The capacitance showed are also called interelectrode capacitance which are external to the device.

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1.3.2 Parasitic Resistance

Comparable to the parasitic capacitance, an increasing influence of parasitic resistance can be observed by decreasing the active region width and therefore the impedance of the device. The most important effect for the parasitic resistance will be the source-drain resistance RSD. The reduction of the transconductance by the source-drain resistance is given by

Equation -1

The gain bandwidth product and propagation delay can be obtained from the following equations

 

Equation -2

The influence of the parasitic resistance expressed by the time constant RSD× CIN is directly added to the transit time t . In this way, the source-drain resistance influence can be very drastic to the performance of a device and maybe the determing factor which limits performance. The location of the parasitic resistances RS, RD, RSD and RG is shown in Figure 0-1.

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1.4 Models

The following models are basing on a general description. Therefore analytic and empirical derivations can be used. Firstly two important device parameters should be introduced. The transconductance gm and the channel conductance or also called drain conductance gD. These equations are given by

       

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1.4.1 Charge Based Model for Circuit Simulation

The Charge Base Model [2] is basing on Equation 5.1.5-1. In any circuit simulation program, the transient response of a circuit is computed by solving numerically nonlinear differential equations which are in fact the node equation of the circuit. This can be done based on different integration methods like the Backward Euler method or the trapezoidal method. An easy method to avoid this method is the backward difference term expressed by

where h is the step width and is responsible for the accuracy and therefore for the extent of computing work.

        Equation 5.1.5-1 is becoming to

        Equation -1

where

        Equation -2

and etc.

These expressions are substituted into Equation 0-1 so that each terminal current is now a function of the node voltages at tk+1 which are the variables of the node equations of the circuit. The equation system is than be solved by Newton iteration to get the node voltages at tk+1.

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1.4.2 Capacitance Based Model

Compared to the Charge Based Model, the Capacitance Based Model is more useful in deriving circuit properties about the MESFET by representing the high frequency or high speed transient behavior in terms of capacitance. Equation 5.1.5-1 shows a model that is dependent on each other because of iD+iG+iS=0. To achieve an equation system that is independent from each other only the first and last equation of Equation 5.1.5-1 is used and however all terminal charges will be expressed in terms of the gate-to-drain VGD and gate-to-source VGS voltages to replace the equation for the gate current. Therefore we get

        Equation -1

where

        Equation -2

so that all capacities are functions of the voltages.

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1.4.3 Small Signal Model

To develop a simple picture for high frequency response of the MESFET, the Small Signal Model is used. The equivalent circuit of a MESFET is shown in Figure 5.4.3-1. The elements CGD and CGS represent the total gate-to-channel capacitance CG. The input resistance Ri and RDS under the gate show the effects of the channel resistance. The parasitic elements are described by the source resistance RS, the drain resistance RD and the substrate capacitance CDS. Out of this model, the various terms for the Small Signal Model will be derived. By changing the voltages at the terminals with the time, the depletion height and hence the amount of charge on the gate and in the channel will change. If D t is the time taken by the device to respond to this change, the change of the channel current is

, Equation -1,

where ID is the source-drain current. The time D t can be interpreted as the average transit time ttr for the carriers to move through the device. The MESFET transconductance can be related to the transit time. General, the transconductance is expressed

Equation -2

and can be derived to

Equation -3

where CG is the gate to channel capacitance which can be expressed by or through addition of CGS and CGD. QG is expressed in Equation 5.1.5-17, VD is the applied voltage along the gate. Equation 5.4.3-3 expresses that the transconductance is indirect proportional to the transit time of the carriers through the device.

The output conductance is given by

 

Equation -4

which describes the effect of the applied source-drain voltage on the drain current.

 

The input resistance Ri is given byand has a value for IG driven against zero and at room temperature of about 250 MW . The MESFET has obviously a very high input resistance and is therefore suitable for amplify applications.

 

Figure -1: physical origin of the circuit elements

The source and the drain resistance are in series and cannot be influenced by the gate voltages. This resistances cause an I× R drop between the gate and the source and drain contacts. This I× R drop will reduce the drain or channel conductance. Therefore it is convenient for this model to express as the intrinsic part [VSD-ID× (RS+RD)] of the voltage and for the gate voltage as [VG-ID× RS]. This voltage drop was not mentioned previously because only the intrinsic part under the gate was regarded.

In the linear region of the I-V curve, the resistances RS, RD and the intrinsic resistance 1/gD0 are in series where gD0 is the channel conductance in the linear region of the I-V curve. Hence the channel or drain conductance is given by

Equation -5.

In the saturation region of the I-V curve, the transconductance is affected only by the source resistance. The drain resistance RD will cause an increase of the drain voltage at which current saturation occurs. Beyond the voltage VD>VD sat, an increasing value of VD does not affect the drain current and therefore it can be assumed that RD has no further effect on the transconductance gm so that the transconductance through the MESFET becomes to

Equation -6.

Under high-frequency operations there are two limiting factors for the frequency response. The transit time of the carriers through the MESFET is one limiting factor and is hence strongly related to device dimensions. The other time factor is caused by capacities in the MESFET and is given by R× C time constant. For the constant mobility and saturated velocity case, the transit time is given by

Equation -7

and for the saturated drift velocity case

Equation -8

To give an idea, for a 1 m m gate in the range of t » 10 ps that is much smaller than the R× CGS time constant and even more so when the interconnect capacitance is included.

A current cutoff frequency fT is defined as the frequency at which the current through CGS is equal to the current generator gm× VG in the intrinsic MESFET.

Equation -9

The maximum frequency fT max is given by

Equation -10

where r1 is the input-to-output resistance ratio, evaluated as

Equation -11

and t * is a time constant given by

Equation -12.

In order to achieve maximum frequency, the extrinsic resistances RG and RS and the feedback capacitance CGD must be minimized, the frequency fT and the resistance ratio Ri/RDS has to be optimized in the intrinsic MESFET.

The intrinsic MESFET can than be described as

 

Equation -13

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1.4.4 Empirical Model

The circuit topology of an empirical model is often also based on the device geometry. The equations are chosen for their concise description of the most important device characteristics. As previously mentioned, these equations may not have any physical origin, rather they describe the device behavior in a mathematical sense. An important advantage of an empirical model is the flexibility. The equations can be fitted over given bias frequency ranges.

Many simplified models have been proposed. All are based on fitting the measured current to a functional description of the current. One of the popular model is that of Statz and it has been installed in HSPICE. In the Statz model, the drain current is given by

Equation: drain current in Statz-Model

This empirical model can be used in the formerly discussed model like the Charge-Based Model, introduced in section 5.4.1.

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1.5 Summary

In this chapter, a MESFET based on GaAs was discussed from the basics. A general idea was given of an analytic model based on physical principles, parasitic influences and different circuit models. In the derivation of equations, many assumptions have to be made to create a model that is suitable for the specific problem. There are many other models which are basing on different velocity-field relations or on a more complete description of the conduction process. This chapter gives an idea how the mathematical way goes and describes both physical and empirical solutions.

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2. Conclusion

This paper was done in partial fulfillment of the requirements for the second practical semester of Microsystem Technology. The different composition of the topics represents my work done during my stay at the Colorado State University, Department of Optoelectronic Devices under head office of Dr. Carl W. Wilmsen, Fort Collins.

This report is a treatise on different aspects such as on-chip and free-space interconnection, smart pixel, a smart pixel based holographic database filter with description of the components and an analytic description of a GaAs MESFET. Holographic memories and their application was since a field of interest of myself. This chapter 3 was additional inspired through new application seen at conferences in Boulder, Co and applications done at CSU, Fort Collins. The designed 8x8 chip array introduced in Chapter 4 was done in team work with Eric Hayes. This development represents the current development in this laboratory. After the aligning of VCSELs on the smart pixel, the application can go into its test phase. Through the theoretical character of Chapter 5 on the physical principles of a GaAs MESFET, my studies in Germany were additional supported and gave to me a new insight to the semiconductor material GaAs and represents thus a balance between Silicon and GaAs for me. Through attending a class in optoelectronics, parts of my work became more easily.

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REFERENCES

  • [1] Christopher Tocci, John Caulfield: Optical Interconnection - Foundations and Applications, Artech House Publishers
  • [2] Omar Wing: Gallium Arsenide Digital Circuits, Kluwer Academic Publishers
  • [3] Robert Anholt: Electrical and Thermal Characterization of MESFETs, HEMTs, and HPTs, Artech House Publishers
  • [4] Jasprit Singh: Electronics and VLSI Circuits, McGraw-Hill
  • [5] Jan Rabaey: Digital Integrated Circuits, Prentice Hall
  • [6] S. M. Sze: Physics of Semiconductor Devices, John Wiley & Sons
  • [7] Grubin, Ferry and Jacoboni: The Physics of Submicron Semiconductor Devices, NATO ASI Series
  • [8] M. S. Tyagi: Introduction to Semiconductor Materials and Devices, John Wiley & Sons
  • [9] Foundry Design Manual Version 6.0, Vitesse
  • [10] Steward Feld, Dissertation Ph.D., Colorado State University, 1996
  • [11] Rick Snyder, Thesis, Colorado State University, 1996

 


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karl@vlsi.bu.edu, 16.09.98